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? semiconductor ML9044 1/54 ? semiconductor ML9044 dot matrix lcd controller driver e2b0055-19-61 this version: jun. 1999 preliminary general description the ML9044 used in combination with an 8Cbit or 4Cbit microcontroller controls the operation of a character type dot matrix lcd. features ? easy interfacing with 8Cbit or 4Cbit microcontroller ? switchable between serial and parallel interfaces ? dotCmatrix lcd controller/driver for a small (5 7 dots) or large (5 10 dots) font ? builtCin circuit allowing automatic resetting at powerCon ? builtCin 17 common signal drivers and 120 segment signal drivers ? builtCin character generation rom capable of generating 160 small characters (5 7 dots) or 32 large characters (5 10 dots) ? creation of character patterns by programming: up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots) ? builtCin rc oscillation circuit using external or internal resistors ? programCselectable duties: 1/9 duty (1 line: 5 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 7 dots + cursor + arbitrator) ? builtCin bias dividing resistors to drive the lcd ? biCdirectional transfer of segment outputs ? biCdirectional transfer of common outputs ? equipped with a 120Cdot arbitrator ? display shifting on each line ? builtCin contrast control circuit ? builtCin voltage multiplier circuit ? chip (gold bump) product name : ML9044cvwa
? semiconductor ML9044 2/54 block diagram v dd gnd osc 1 osc r osc 2 rs1 rs0 r/ w e cs p /s sht si so db 0 to db 3 4 db 4 to db 7 4 t 1 t 2 t 3 v 1 v 2 v 3b v 3a v 4 v 5 v 5in timing generator 8 i/o buffer 8 instruction register (ir) instruction decoder (id) 7 8 8 8 data register (dr) 5 com 1 seg 1 com 17 test circuit lcd bias voltage dividing circuit 5 8 busy flag (bf) expansion instruction register (er) voltage multiplier circuit address counter (adc) expansion instruction decoder (ed) character generator rom (cgrom) 8 8 display data ram (ddram) arbitrator ram (abram) character generator ram (cgram) cursor blink controller 5 5 csr 17-bit shift register common signal driver rarallel- serial converter 120-bit shift register 120-bit latch segment signa - driver seg 120 ssr beb v cc v c v in
? semiconductor ML9044 3/54 i/o circuits v dd p n applied to pins e, ssr, csr, beb, cs p /s, sht , and si v dd p n applied to pins t 1 , t 2 , and t 3 v dd p n v dd applied to pins r/ w , rs 1 , and rs 0 v dd p v dd p n v dd p n applied to pins db0 to db7 output enable signal v dd pp v dd n applied to pins so output enable signal
? semiconductor ML9044 4/54 pin descriptions symbol description r/ w the input pin with a pullCup resistor to select read (h) or write (l) in the parallel i/f mode. this pin should be open in the serial i/f mode. rs 0 , rs 1 rs 1 rs 0 name of register h h data register h l instruction register l l expansion instruction register the input pins with a pullCup resistorC to select a register in the parallel i/f mode. this pin should be open in the serial i/f mode. e the input pin for data input/output between the cpu and the ML9044 and for activating instructions in the parallel i/f mode. this pin should be open in the serial i/f mode. db 0 to db 3 the input/output pins to transfer data of lowerCorder 4 bits between the cpu and the ML9044 in the parallel i/f mode. each pin is equipped with a pullCup resistor. these 4 lines are not used for the 4Cbit interface. this pin should be open in the serial i/f mode. db 4 to db 7 the input/output pins to transfer data of upper 4 bits between the cpu and the ML9044 in the parallel i/f mode. each pin is equipped with a pullCup resistor. this pin should be open in the serial i/f mode. osc 1 osc 2 osc r the clock oscillation pins required for lcd drive signals and the operation of the ML9044 by instructions sent from the cpu. to input external clock, the osc 1 pin should be used. the osc r and the osc 2 pins should be open. to start oscillation with an external resistor, the resistor should be connected between the osc 1 and osc 2 pins. the osc r pin should be open. to start oscillation with an internal resistor, the osc 2 and osc r pins should be shortCcircuited outside the ML9044. the osc 1 pin should be open. com 1 to com 17 the lcd common signal output pins. for 1/9 duty, nonCselectable voltage waveforms are output via com 10 to com 17 . for 1/12 duty, nonCselectable voltage waveforms are output via com 13 to com 17 . seg 1 to seg 120 the lcd segment signal output pins.
? semiconductor ML9044 5/54 ssr the input pin to select the transfer direction of the segment signal output data. l: data transfer from seg 1 to seg 120 h: data transfer from seg 120 to seg 1 v 1 , v 2 , v 3a , v 3b , v 4 the pins to output bias voltages to the lcd. for 1/4 bias : the v 2 and v 3b pins are shorted. for 1/5 bias : the v 3a and v 3b pins are shorted. beb the input pin to enable or disable the voltage multiplier circuit. l disables the voltage multiplier circuit. h enables the voltage multiplier circuit. the voltage multiplier circuit doubles the input voltage v in and outputs it to the v 5in pin. the voltage multiplier circuit can be used only when generating a level lower than gnd. v in the pin to input voltage to the voltage multiplier. v 5 , v 5in the pins to supply the lcd drive voltage. the lcd drive voltage is supplied to the v 5 pin when the voltage multiplier is not used (beb = 0) and the internal contrast adjusting circuit is also not used. at this time, the v 5in pin should be open. the lcd drive voltage is supplied to the v 5in pin when the voltage multiplier is not used (beb = 0) but the internal contrast adjusting circuit is used. at this time, the v 5 pin should be open. when the voltage multiplier is used (beb = 1), the v 5in and v 5 pins should be open (the multiplied voltage is output to the v 5in pin). in this case, the internal contrast adjusting circuit is used automatically. v c the pin to connect the positive pin of the capacitor for the voltage multiplier. v cc the pin to connect the negative pin of the capacitor used for the voltage multiplier. csr the input pin to select the transfer direction of the common signal output data. refer to the expansion instruction codes section about the as bit. csr duty as bit shift direction arbitrator's common pin l 1/9 l com1 ? com9 com9 l 1/9 h com2 ? com9, com1 com1 l 1/12 l com1 ? com12 com12 l 1/12 h com2 ? com12, com1 com1 l 1/17 l com1 ? com17 com17 l 1/17 h com2 ? com17, com1 com1 h 1/9 l com9 ? com1 com1 h 1/9 h com8 ? com1, com9 com9 h 1/12 l com12 ? com1 com1 h 1/12 h com11 ? com1, com12 com12 h 1/17 l com17 ? com1 com1 h 1/17 h com16 ? com1, com17 com17 symbol description
? semiconductor ML9044 6/54 p /s the input pin to select the parallel or serial interface. l selects the parallel interface. h selects the serial interface. cs the pin to enable this ic in the serial i/f mode. l enables this ic. h disables this ic. this pin should be open in the parallel i/f mode. sht the pin to input shift clock in the serial i/f mode. data inputting to the si pin is carried out synchronizing with the rising edge of this clock signal. data outputting from the so pin is carried out synchronizing with the falling edge of this clock signal. this pin should be open in the parallel i/f mode. si the pin to input data in the serial i/f mode. data inputting to this pin is carried out synchronizing with the rising edge of the sht signal. this pin should be open in the parallel i/f mode. so the pin to output data in the serial i/f mode. data inputting to this pin is carried out synchronizing with the falling edge of the sht signal. this pin should be open in the parallel i/f mode. symbol description t 1 , t 2 , t 3 the input pins for test circuits (normally open). equipped with a pullCdown resistor. v dd the power supply pin. gnd the ground level input pin.
? semiconductor ML9044 7/54 absolute maximum ratings note: this voltage should be applied across v dd and v 5 . the following voltages are output to the v 1 , v 2 , v 3a (v 3b ) and v 4 pins: ? 1/4 bias v 1 = {v dd C(v dd Cv 5 )/4} 0.15v v 2 = v 3b = {v dd C(v dd Cv 5 )/2} 0.15v v 4 = {v dd C3 (v dd Cv 5 )/4 } 0.15v ? 1/5 bias v 1 = {v dd C(v dd Cv 5 )/5} 0.15v v 2 = {v dd C2 (v dd Cv 5 )/5} 0.15v v 3a = v 3b = {v dd C3 (v dd Cv 5 )/5} 0.15v v 4 = {v dd C4 (v dd Cv 5 )/5} 0.15v the voltages at the v 1 , v 2 , v 3a (v 3b ), v 4 and v 5 pins should satisfy v dd > v 1 > v 2 > v 3a (v 3b ) > v 4 > v 5 . (higher ?? lower) * do not apply shortCcircuiting across output pins and across an output pin and an input/output pin or the power supply pin in the output mode. recommended operating conditions parameter symbol condition rating unit applicable pins (gnd = 0v) supply voltage v dd ta = 25c C0.3 to +6.5 v v dd C gnd lcd driving voltage v 1 , v 2 , v 3 , v 4 , v 5 ta = 25c v dd C 7.5 to v dd +0.3 v v 1 , v 4 , v 5 , v 5in , v 2 , v 3a , v 3b input voltage v i ta = 25c C0.3 to v dd +0.3 v r/ w , e, sht , csr, p /s, ssr, si, rs 0 , rs 1 , beb, cs , t 1 to t 3 , db 0 to db 7 , v in storage temperature t stg C55 to +125 c parameter symbol condition range unit applicable pins (gnd = 0v) supply voltage v dd 2.5 to 5.5 v v dd Cgnd input voltage v in beb = 1 v dd C1.40 to v dd C3.5 vv dd Cv in lcd driving voltage v dd Cv 5 (see note) 2.8 to 7.0 v v dd Cv 5 (v 5 in ) operating temperature t op C40 to +85 c
? semiconductor ML9044 8/54 electrical characteristics dc characteristics (gnd = 0v, v dd = 2.5v to 5.5v, ta = C40 to +85c) parameter symbol condition min typ max unit applicable pin h input voltage 1 v ih1 0.8v dd v dd v l input voltage 1 v il1 C0.3 0.2v dd h input voltage 2 v ih2 0.8v dd v dd v l input voltage 2 v il2 C0.3 0.2v dd h output voltage 1 v oh1 i oh = C0.1ma 0.75v dd v l output voltage 1 v ol1 i ol = +0.1ma 0.2v dd h output voltage 2 v oh2 i oh = C13 m a 0.9v dd v l output voltage 2 v ol2 i ol = +13 m a 0.1v dd com voltage drop v ch i och = C4 m av dd C 0.3 v dd v v cmh i ocmh = 4 m a v 1 C 0.3 v 1 + 0.3 v cml i ocml = 4 m a v 4 C 0.3 v 4 + 0.3 v cl i ocl = +4 m av 5 v 5 + 0.3 seg voltage drop v sh i osh = C4 m av dd C 0.3 v dd v v smh i osmh = 4 m a v 2 C 0.3 v 2 + 0.3 v sml i osml = 4 m a v 3 C 0.3 v 3 + 0.3 v sl i osl = +4 m a v dd Cv 5 = 5v v dd C v 5 = 5v note 1 note 1 v 5 v 5 + 0.3 input leakage current | iil | v dd = 5v, v in = 5v or 0v 1.0 m a input current 1 | ii1| v dd = 5v, v i n = gnd 10 25 61 m a v dd = 5v, v i n = v dd , excluding current flowing through the pull-up resistor and the output driving mos 2.0 input current 2 | ii2| v dd = 5v, v i n = v dd 15 45 105 m a v dd = 5v, v i n = v dd , excluding current flowing through the pull-down resistor 2.0 supply current i dd v dd = 5v note 2 rf = 120k w 2% note 3 osc 1 : open osc 2 and osc r : short-circuited note 4 osc 2 , osc r : open input from osc 1 1.2 ma lcd bias resistor r lb 4.0 k w oscillation frequency of external resistor rf f osc1 175 270 350 khz oscillation frequency of internal resistor rf f osc2 140 270 480 khz clock input frequency input clock rise time external clock f in 125 480 khz input clock duty f duty note 5 45 50 55 % f rf note 6 0.2 m s f ff note 6 0.2 m s e, ssr, csr, beb, sht , p /s, cs, si r/ w , rs 0 , rs 1 db 0 to db 7 , so t 1 , t 2 , t 3 v dd C gnd v dd , v 1 , v 2 v 3a , v 3b , v 4 , v 5 osc 1 , osc 2 osc 1 , osc 2 , osc r osc 1 r/ w , rs 0 , rs 1 , e, db 0 to db 7 sht , p /s, si, cs osc 1 , ssr, csr, beb db 0 to db 7 , so osc 2 com 1 to com 17 seg 1 to seg 120 input clock fall time
? semiconductor ML9044 9/54 control range of lcd driving voltage (by internal variable resistor) v lcd max v dd = 5v, 1/5 bias v 5in = 0v tbd v lcd min v dd = 5v, 1/5 bias v 5in = 0v tbd bias voltage for driving lcd by external input v lcd1 v dd C v5 2.8 7.0 v v lcd2 note 7 1/5 bias 1/4 bias 2.8 7.0 voltage multiplier output voltage v5out v dd = 3v, v in = 0v beb = h v dd C 2v in v dd C2v in +1.2v v voltage multipler input voltage v in v dd /2 v v dd C v 5 v 5 v 5 , v 5in v in (gnd = 0v, v dd = 2.5v to 5.5v, ta = C40 to +85c) parameter symbol condition min typ max unit applicable pin
? semiconductor ML9044 10/54 note 1: applied to the voltage drop occurring between any of the v dd , v 1 , v 4 and v 5 pins and any of the common pins (com 1 to com 17 ) when the current of 4 m a flows in or flows out at one common pin. also applied to the voltage drop occurring between any of the v dd , v 2 , v 3a (v 3b ) and v 5 pins and any of the segment pins (seg 1 to seg 120 ) when the current of 4 m a flows in or flows out at one common pin. the current of 4 m a flows out when the output level is v dd or flows in when the output level is v 5 . note 2: applied to the current flowing into the v dd pin when the external clock (f osc2 = f in = 270 khz) is fed to the internal r f oscillation or osc 1 under the following conditions: v dd = 5v gnd = v 5 = 0v, v 1 , v 2 , v 3a (v 3b ) and v 4 : open e, ssr, csr, and beb: l (fixed) other input pins: l or h (fixed) other output pins: no load osc 1 osc r osc 2 the wire between osc 2 and osc r should be as short as possible. keep osc 1 open. osc 1 osc r osc 2 the wire between osc 1 and r f and the wire between osc 2 and r f should be as short as possible. keep osc r open. r f = 120k w 2% t hw t lw v dd 2 f in waveform v dd 2 v dd 2 applied to the pulses entering from the osc 1 pin f duty = t hw / (t hw + t lw ) 100 (%) note 3: note 4: note 5:
? semiconductor ML9044 11/54 note 7: for 1/4 bias, v 2 and v 3b pins are shortCcircuited. v 3a pin is open. for 1/5 bias, v 3a and v 3b pins are shortCcircuited. v 2 pin is open. note 6: 0.7v dd applied to the pulses entering from the osc 1 pin 0.7v dd 0.3v dd 0.3v dd t rf t ff
? semiconductor ML9044 12/54 switching characteristics (the following ratings are subject to change after es evaluation.) ? parallel interface mode the timing for the input from the cpu (see 1) and the timing for the output to the cpu (see 2) are as shown below: 1) write mode (timing for input from the cpu) (v dd = 2.5 to 5.5v, ta = C40 to +85c) parameter symbol unit min typ max r/ w , rs 0 , rs 1 setup time 40 t b ns e pulse width 450 t w ns r/ w , rs 0 , rs 1 hold time 10 t a ns e rise time 25 t r ns e fall time 25 t f ns e pulse width 430 t l ns e cycle time 1000 t c ns db 0 to db 7 input data hold time 195 t i ns db 0 to db 7 input data setup time 10 t h ns rs 1 , rs 0 v ih v il v ih v il v il v il v il v il v il v ih v ih v ih v il v ih v il r/ w e db 0 to db 7 t l t b t w t r t f t a t h t i input data t c
? semiconductor ML9044 13/54 2) read mode (timing for output to the cpu) (v dd = 2.5 to 5.5v, ta = C40 to +85c) parameter symbol unit min typ max r/ w , rs 1 , rs 0 setup time 40 t b ns e pulse width 450 t w ns r/ w , rs 1 , rs 0 hold time 10 t a ns e rise time 25 t r ns e fall time 25 t f ns e pulse width 430 t l ns e cycle time 1000 t c ns db 0 to db 7 output data delay time 350 t d ns db 0 to db 7 output data hold time 20 t o ns rs 1, 0 v ih v il v ih v il v ih v ih v il v il v il v ih v ih v oh v ol v oh v ol r/ w e db 0 to db 7 t l t b t w t r t f t a t o t d output data t c
? semiconductor ML9044 14/54 ? serial interface mode (v dd = 2.5 to 5.5v, ta = C40 to +85c) parameter symbol unit min typ max sht cycle time 500 t scy ns cs setup time 100 t csu ns cs hold time 100 t ch ns sht setup time 60 t ssu ns sht hold time 200 t sh ns sht "h" pulse width 200 t swh ns sht "l" pulse width 200 t swl ns sht rise time 50 t sr ns sht fall time 50 t sf ns si setup time 100 t disu ns si hold time 100 t dih ns data output delay time 160 t dod ns data output hold time 0 t cdh ns v ih v il v ih v il si v il t scy t dod t dod v ol v oh v oh t cdh cs so sht t csu t ssu t swl t sr t swh t sf t sh t ch v ih v il v ih v ih v ih v il t disu t dih
? semiconductor ML9044 15/54 functional description instruction register (ir), data register (dr), and expansion instruction register (er) these registers are selected by setting the level of the register selection input pins rs 0 and rs 1 . the dr is selected when both rs 0 and rs 1 are h. the ir is selected when rs0 is l and rs 1 is h. the er is selected when both rs 0 and rs 1 are l. (when rs 0 is h and rs 1 is l, the ML9044 is not selected.) the ir stores an instruction code and the address code of the display data ram (ddram) or the character generator ram (cgram). the microcontroller (cpu) can write to the ir but cannot read from the ir. the er stores a contrast adjusting code and the address code of the arbitrator ram (abram). the cpu can write to or read from the er. the dr stores data to be written in the ddram, abram and cgram and also stores data read from the ddram, amram and cgram. the data written in the dr by the cpu is automatically written in the ddram, abram or cgram. when an address code is written in the ir or er, the data of the specified address is automatically transferred from the ddram, abram or cgram to the dr. the data of the ddram, abram and cgram can be checked by allowing the cpu to read the data stored in the dr. after the cpu writes data in the dr, the data of the next address in the ddram, abram or cgram is selected to be ready for the next writing by the cpu. similarly, after the cpu reads the data in the dr, the data of the next address in the ddram, abram or cgram is set in the dr to be ready for the next reading by the cpu. writing in or reading from these 3 registers is controlled by changing the status of the r/ w (read/write) pin. table 1 r/ w pin status and register operation busy flag (bf) the status 1 of the busy flag (bf) indicates that the ML9044 is carrying out internal operation. when the bf is 1, any new instruction is ignored. when r/ w = h, rs 0 = l and rs 1 = h, the data in the bf is output to the db 7 . new instructions should be input when the bf is 0. when the bf is 1, the output code of the address counter (adc) is undefined. r/ w rs 0 rs 1 operation writing in the ir llh reading the busy flag (bf) and the address counter (adc) hlh writing in the dr lhh reading from the dr hhh writing in the er lll reading the contrast code hll
? semiconductor ML9044 16/54 address counter (adc) the address counter provides a read/write address for the ddram, abram or cgram and also provides a cursor display address. when an instruction code specifying ddram, abram or cgram address setting is input to the preCdefined register, the register selects the specified ddram, abram or cgram and transfers the address code to the adc. the address data in the adc is automatically incremented (or decremented) by 1 after the display data is written in or read from the ddram, abram or cgram. the data in the adc is output to db 0 to db 6 when r/ w = h, rs 0 = l, rs 1 = h and bf = 0. timing generator the timing generator generates timing signals for the internal operation of the ML9044 activated by the instruction sent from the cpu or for the operation of the internal circuits of the ml9041 such as ddram, abram, cgram and cgrom. timing signals are generated so that the internal operation carried out for lcd displaying will not be interfered by the internal operation initiated by accessing from the cpu. for example, when the cpu writes data in the ddram, the display of the lcd not corresponding to the written data is not affected.
? semiconductor ML9044 17/54 display data ram (ddram) this ram stores the display data represented in 8Cbit character coding (see table 2). the ddram addresses correspond to the display positions (digits) of the lcd as shown below. the ddram addresses (to be set in the adc) are represented in hexadecimal. msb lsb db 6 db 5 db 4 db 3 db 2 db 1 db 0 hexadecimal hexadecimal 2 0 adc 0 1 0 0 1 0 1 adc (example) representation of ddram address = 12 00 01 02 03 04 16 17 digit 2 3 4 5 23 24 left end right end display position dd ram address (hexadecimal) 1 4f 00 01 02 15 16 digit 234 2324 (display shifted to the right) 1 01 02 03 04 17 18 digit 234 05 52324 (display shifted to the left) 1 1) relationship between ddram addresses and display positions (1Cline display mode) in the 1Cline display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24. while the ddram has addresses 00 to 4f for up to 80 character codes, the area not used for display can be used as a ram area for general data. when the display is shifted by instruction, the relationship between the lcd display and the ddram address changes as shown below:
? semiconductor ML9044 18/54 2) relationship between ddram addresses and display positions (2Cline display mode) in the 2Cline mode, the ML9044 can display up to 48 characters (24 characters per line) from digit 1 to digit 24. 00 01 02 03 04 digit 2345 16 17 23 24 40 41 42 43 44 56 57 line 1 line 2 display position dd ram address (hexadecimal) 1 27 00 01 02 1234 15 16 23 24 67 40 41 42 55 56 line 1 line 2 01 02 03 04 1234 17 18 23 24 41 42 43 44 03 5 43 05 5 45 57 58 line 1 line 2 (display shifted to the right) (display shifted to the left) digit digit note: the ddram address at digit 24 in the first line is not consecutive to the ddram address at digit 1 in the second line. when the display is shifted by instruction, the relationship between the lcd display and the ddram address changes as shown below:
? semiconductor ML9044 19/54 character generator rom (cgrom) the cgrom generates small character patterns (5 7 dots, 160 patterns) or large character patterns (5 10 dots, 32 patterns) from the 8Cbit character code signals in the ddram. see table 2 for the relationship between the 8Cbit character codes and the character patterns. when the 8Cbit character code corresponding to a character pattern in the cgrom is written in the ddram, the character pattern is displayed in the display position specified by the ddram address.
? semiconductor ML9044 20/54 character generator ram (cgram) the cgram is used to generate userCspecific character patterns that are not in the cgrom. cgram (64 bytes = 512 bits) can store up to 8 small character patterns (5 8 dots) or up to 4 large character patterns (5 11 dots). when displaying a character pattern stored in the cgram, write an 8Cbit character code (00 to 07 or 08 to 0f; hex.) assigned in table 2 to the ddram. this enables outputting the character pattern to the lcd display position corresponding to the ddram address. the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is holding a cgram or abram address. the following describes how character patterns are written in and read from the cgram. 1) small character patterns (5 8 dots) (see table 3C1.) (1) a method of writing character patterns to the cgram from the cpu the three cgram address bits 0 to 2 select one of the lines constituting a character pattern. first, set the mode to increment or decrement from the cpu, and then input the cgram address. write each line of the character pattern code in the cgram through db 0 to db 7 . the data lines db0 to db7 correspond to the cgram data bits 0 to 7, respectively (see table 3.1). input data 1 represents the on status of an lcd dot and 0 represents the off status. since the adc is automatically incremented or decremented by 1 after the data is written to the cgram, it is not necessary to set the cgram address again. the bottom line of a character pattern (the cgram address bits 0 to 2 are all 1, which means 7 in hexadecimal) is the cursor line. the on/off pattern of this line is ored with the cursor pattern for displaying on the lcd. therefore, the pattern data for the cursor position should be all zeros to display the cursor. whereas the data given by the cgram data bits 0 to 4 is output to the lcd as display data, the data given by the cgram data bits 5 to 7 is not. therefore, the cgram data bits 5 to 7 can be used as a ram area. (2) a method of displaying cgram character patterns on the lcd the cgram is selected when the higherCorder 4 bits of a character code are all zeros. since bit 3 of a character code is not used, the character pattern 0 in table 3C1 can be selected using the character code 00 or 08 in hexadecimal. when the 8Cbit character code corresponding to a character pattern in the cgram is written to the ddram, the character pattern is displayed in the display position specified by the ddram address. (the ddram data bits 0 to 2 correspond to the cgram address bits 3 to 5, respectively.)
? semiconductor ML9044 21/54 2) large character patterns (5 11 dots) (see table 3C2.) (1) a method of writing character patterns to the cgram from the cpu the four cgram address bits 0 to 3 select one of the lines constituting a character pattern. first, set the mode to increment or decrement from the cpu, and then input the cgram address. write each line of the character pattern code in the cgram through db 0 to db 7 . the data lines db 0 to db 7 correspond to the cgram data bits 0 to 7, respectively (see table 3C 2). input data 1 represents the on status of an lcd dot and 0 represents the off status. since the adc is automatically incremented or decremented by 1 after the data is written to the cgram, it is not necessary to set the cgram address again. the bottom line of a character pattern (the cgram address bits 0 to 3 are all 1, which means a in hexadecimal) is a cursor line. the on/off pattern of this line is ored with the cursor pattern for displaying on the lcd. therefore, the pattern data for the cursor position should be all zeros to display the cursor. whereas the data given by the cgram data bits 0 to 4 with the cgram addresses 0 to a in hexadecimal (set by the cgram address bits 0 to 3) is output as display data to the lcd, the data given by the cgram data bits 5 to 7 or the cgram addresses b to f in hexadecimal is not. these bits can be written and read as a ram area. (2) a method of displaying cgram character patterns on the lcd the cgram is selected when the higherCorder 4 bits of a character code are all zeros. since bits 0 and 3 of a character code are not used, the character pattern b in table 3C2 can be selected with a character code 00, 01, 08 or 09 in hexadecimal. when the 8Cbit character code corresponding to a character pattern in the cgram is written to the ddram, the character pattern is displayed in the display position specified by the ddram address. (the ddram data bits 1 and 2 correspond to the cgram address bits 4 and 5, respectively.)
? semiconductor ML9044 22/54 arbitrator ram (abram) the arbitrator ram(abram) stores arbitrator display data. the abram address is set at the adc with the relationship illustrated below. its valid address area is 00 to 23 (00h to 17h). although an address exceeding 23 (17h) can be set or the address already set may exceed it due to automatic increment or decrement processing, any address out of the valid address area is ignored. the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is hoding a cgram or abram address. msb lsb db 6 db 5 db 4 db 3 db 2 db 1 db 0 hexadecimal hexadecimal adc * * e4 e3 e2 e1 e0 db 6 * db 7 db 5 db 4 db 3 db 2 db 1 db 0 * don't care display - on data e4 e4 5xsn+1 5xsn+5 configuration of input display data input data relationship between display-on data and segment pins sn = abram address ( 0 to 23 ) the arbitrator ram can store a maximum of 120 dots of the arbitrator displayCon data in units of 5 dots. the arbitrator display is not shifted by any instructions and has the following relationship with the lcd display positions:.
? semiconductor ML9044 23/54 table 2 relationship between character codes and character patterns of the ML9044 lower 4 bits upper 4 bits 0000 lsb 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 msb 0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111 0001 cg ram (1) (3) (4) (5) (6) (7) (8) (1) (2) (3) (4) (5) (9) (7) (8) (2) # $ % & ( ) * + C . / ! 2 3 4 5 6 7 8 9 : ; < = > ? 1 0 b c d e f g h i j k l m n o a @ r s t u v w x y z [ ] ^ _ q p b c d e f n h i j k l m n o a / r s t u v w x y z { ? } ? ? q p b e m s r g C1 j x n ? ? a q w s p x q r ?
? semiconductor ML9044 24/54 table 3C1 relationship between cgram address bits, cgram data bits (character pattern) and ddram data bits (character code) in 5 7 dot character mode. (examples) cg ram cg ram address (character pattern) (character code) data dd ram data 543210 000000 001 010 011 100 101 110 111 01110 10001 10001 10001 10001 10001 01110 00000 76543210 76543210 msb lsb msb lsb msb lsb 0000 000 001000 001 010 011 100 101 110 111 10001 10010 10100 11000 10100 10010 10001 00000 0000 001 111000 001 010 011 100 101 110 111 01110 00100 00100 00100 00100 00100 01110 00000 0000 111 : don't care
? semiconductor ML9044 25/54 table 3C2 relationship between cgram address bits, cgram data bits (character pattern) and ddram data bits (character code) in 5 10 dot character mode (examples) cg ram cg ram address (character pattern) (character code) data dd ram data 543210 76543210 76543210 lsb msb msb lsb msb lsb 0000 00 000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 00 000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00000 00000 01111 10001 10001 10001 01111 00001 00001 01110 00000 0000 11 000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 00000 00000 11011 01010 10001 10001 01110 00000 00000 00000 00000 : don't care 0 01000 01111 10010 01111 01 11111 00010 00000 00000 00000 00000 0 1
? semiconductor ML9044 26/54 cursor/blink control circuit this circuit generates the cursor and blink of the lcd. the operation of this circuit is controlled by the program of the cpu. the cursor/blink display is carried out in the position corresponding to the ddram address set in the adc (address counter). for example, when the adc stores a value of 07 (hexadecimal), the cursor or blink is displayed as follows: note: the cursor or blink is also displayed even when a cgram or abram address is set in the adc. therefore, the cursor or blink display should be inhibited while the adc is holding a cgram or abram address. 0 db6 db0 000111 7 0 00 01 02 03 04 07 08 1234 5 89 cursor/blink position 16 17 23 24 67 05 06 00 01 02 03 04 07 08 1234 5 89 cursor/blink p osition 16 17 23 24 67 05 06 40 41 42 43 44 47 48 56 57 45 46 first line adc in 1-line display mode in 2-line display mode second line digit digit
? semiconductor ML9044 27/54 lcd display circuit (com1 to com17, seg1 to seg120, ssr and csr) the ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24 characters (in the 1Cline display mode) or 48 characters (in the 2Cline display mode). the character pattern is converted into serial data and transferred in series through the shift register. the transfer direction of serial data is determined by the ssr pin. the shift direction of common signals is determined by the csr pin. the following tables show the transfer and shift directions: * refer to the expansion instruction codes section about the as bit. signals to be input to the ssr and csr pins should be determined at powerCon and be kept unchanged. csr duty as bit shift direction arbitrator's common pin l 1/9 l com1 ? com9 com9 l 1/9 h com2 ? com9, com1 com1 l 1/12 l com1 ? com12 com12 l 1/12 h com2 ? com12, com1 com1 l 1/17 l com1 ? com17 com17 l 1/17 h com2 ? com17, com1 com1 h 1/9 l com9 ? com1 com1 h 1/9 h com8 ? com1, com9 com9 h 1/12 l com12 ? com1 com1 h 1/12 h com11 ? com1, com12 com12 h 1/17 l com17 ? com1 com1 h 1/17 h com16 ? com1, com17 com17 ssr transfer direction l seg 1 ? seg 120 h seg 120 ? seg 1
? semiconductor ML9044 28/54 builtCin reset circuit the ML9044 is automatically initialized when the power is turned on. during initialization, the busy flag (bf) is 1 and the ml9041 does not accept any instruction from the cpu (other than the read bf instruction). the busy flag is 1 for about 15 ms after the v dd becomes 2.5 v or higher. during this initialization, the ML9044 performs the following instructions: 1) display clearing 2) cpu interface data length = 8 bits (dl = 1) 3) 1Cline lcd display (n = 0) 4) font size = 5 7 dots (f = 0) 5) adc counting = increment (i/d = 1) 6) display shifting = none (s = 0) 7) display = off (d = 0) 8) cursor = off (c = 0) 9) blinking = off (b = 0) 10) arbitrator = displayed in the lower line (as = 0) 11) setting 1fh (hexadecimal) to the contrast data to use the builtCin reset circuit, the power supply conditions shown below should be satisfied. otherwise, the builtCin reset circuit may not work properly. in such a case, initialize the ML9044 with the instructions from the cpu. the use of a battery always requires such initialization from the cpu. (see initial setting of instructions) figure 1 powerCon and powerCoff waveform t on 2.5v 0.2v 0.2v 0.2v t off 0.1ms t on 100ms 1ms t off
? semiconductor ML9044 29/54 i/f with cpu parallel interface mode the ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8Cbit or 4Cbit microcontroller (cpu). 1) 8Cbit interface data length the ML9044 uses all of the 8 data bus lines db0 to db7 at a time to transfer data to and from the cpu. 2) 4Cbit interface data length the ML9044 uses only the higherCorder 4 data bus lines db 4 to db 7 twice to transfer 8Cbit data to and from the cpu. the ML9044 first transfers the higherCorder 4 bits of 8Cbit data (db 4 to db 7 in the case of 8Cbit interface data length) and then the lowerCorder 4 bits of the data (db 0 to db 3 in the case of 8Cbit interface data length). the lowerCorder 4 bits of data should always be transferred even when only the transfer of the higherCorder 4 bits of data is required. (example: reading the busy flag) two transfers of 4 bits of data complete the transfer of a set of 8Cbit data. therefore, when only one access is made, the following data transfer cannot be completed properly.
? semiconductor ML9044 30/54 figure 2 8-bit data transfer figure 3 4-bit data transfer rs 0 r/ w e busy (internal operation) ir 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 db 7 busy no busy dr 7 ir 6 dr 6 adc 6 ir 5 dr 5 adc 5 ir 4 dr 4 adc 4 ir 3 dr 3 adc 3 ir 2 dr 2 adc 2 ir 1 dr 1 adc 1 ir 0 dr 0 adc 0 rs 1 writing in ir (instruction register) reading bf (busy flag) and adc (address counter) writing in dr (data register) rs 0 r/ w e busy (internal operation) db 7 db 6 db 5 db 4 ir 7 busy no busy dr 7 dr 3 adc 3 adc 5 dr 6 dr 2 adc 2 dr 5 dr 1 adc 1 adc 4 dr 4 dr 0 adc 0 adc 6 ir 3 ir 6 ir 2 ir 5 ir 1 ir 4 ir 0 rs 1 writing in ir (instruction register) reading bf (busy flag) and adc (address counter) writing in dr (data register)
? semiconductor ML9044 31/54 serial interface mode in the serial i/f mode, the ML9044 interfaces with the cpu via the cs , sht , si and so pins. writing and reading operations are executed in units of 16 bits after the cs signal falls down. if the cs signal rises up before the completion of 16Cbit unit access, this access is ignored. when the bf bit is 1, the ML9044 cannot accept any other instructions. before inputting a new instruction, check that the bf bit is 0. any access when the bf bit is 1 is ignored. data format is lsbCfirst. examples of access in the serial i/f mode 1) write mode cs so sht si 12345 11111 6 7 8 9 10 11 12 13 14 15 16 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 rs 1 rs 0 r/ w cs so sht si 12345 11111 6 7 8 9 10 11 12 13 14 15 16 rs 1 rs 0 r/ w d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 2) read mode
? semiconductor ML9044 32/54 instruction codes table of instruction codes display clear cursor home entry mode setting displya on/off control cursor/display shift function setting cgram address setting ddram address setting busy flag/address read ram data write ram data read contrast control data write contrast control data read instruction function execution time f = 270khz code db0 db1 db2 db3 db4 db5 db6 db7 r/ w rs0 rs1 clears all the displayed digits of the lcd and sets the ddram address 0 in the address counter. the arbitrator data is cleared. sets the ddram address 0 in the address counter and shifts the display back to the original. the content of the ddram remains unchanged. determines the direction of movement of the cursor and whether or not to shift the display. this instruction is executed when data is written or read. sets lcd display on/off (d), cursor on/off or cursor-position character blinking on/off. moves the cursor or shifts the display without changing the content of the ddram. sets the interface data length (dl), the number of display lines (n) or the type of character font (f). sets on cgram address. after that, cgram data is transferred to and from the cpu. sets a ddram address. after that ddram data is transferred to and from the cpu. reads the busy flag (indicating that the ML9044 is operating) and the content of the address counter. writes data in ddram, abram or cgram. reads data from ddram, abram or cgram. writes data to control the contrast of the lcd. reads data to control the contrast of the lcd. the execution time is dependent upon frequencies dd ram cg ram abram acg add aab adc : display data ram : character generator ram : arbitrator data ram : cgram address : ddram address (corresponds to the cursor address) : abram address : address counter (used by ddram, abram and cgram) i/d = "0" s/c = "0" r/l = "0" dl = "0" n = "0" f = "0" bf = "0" as = "0" i/d = "1" s = "1" s/c = "1" r/l = "1" d/l = "1" n = "1" f = "1" bf = "1" b = "1" c = "1" d = "1" as = "1" (decrement) (moves the cursor.) (left shift) (4-bit data) (1 line) (5 7 dots) (ready to accept an instruction) (arbitrator displays arbitrator on the lower line) (increment) (shifts the display.) (shifts display.) (right shift) (8-bit data) (2 lines) (5 10 dots) (busy) (enables blinking.) (displyas the corsor.) (displays a character pattern.) (arbitrator displays arbitrator on the upper line) 1.52 ms 1.52 ms 37 m s 37 m s 37 m s 37 m s 37 m s 37 m s 0 m s 37 m s 37 m s 37 m s 37 m s 1 0 0 0 0 0 0 0 0 0 1 * 1 0 0 0 0 0 0 0 0 1 s i/d 1 0 0 0 0 0 0 0 1 b c d 1 0 0 0 0 0 0 1 * * r/l s/c 1 0 0 0 0 0 1 * * f n dl 1 0 0 0 0 1 1 0 0 0 1 1 0 0 1 bf 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 acg add adc write data read data arbitrator display line set sets the arbitrator display line. 37 m s 00000001as 0 0 write (contrast data) data read (contrast data) data abram address setting sets an abram address. after that abram data is transferred to and from the cpu. 37 m s 0 0 01 1 0 aab : don't care
? semiconductor ML9044 33/54 instruction codes an instruction code is a signal sent from the cpu to access the ML9044. the ML9044 starts operation as instructed by the code received. the busy status of the ML9044 is rather longer than the cycle time of the cpu, since the internal processing of the ML9044 starts at a timing which does not affect the display on the lcd. in the busy status (busy flag is 1), the ML9044 executes the busy flag read instruction only. therefore, the cpu should ensure that the busy flag is 0 before sending an instruction code to the ML9044. 1) display clear when this instruction is executed, the lcd display including arbitrator display is cleared and the i/d entry mode is set to increment. the value of s (display shifting) remains unchanged. the position of the cursor or blink being displayed moves to the left end of the lcd (or the left end of the line 1 in the 2Cline display mode). note: all ddram and abram data turn to 20 and 00 in hexadecimal, respectively. the value of the address counter (adc) turns to the one corresponding to the address 00 (hexadecimal) of the ddram. the execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 khz. 2) cursor home when this instruction is executed, the cursor or blink position moves to the left end of the lcd (or the left end of line 1 in the 2Cline display mode). if the display has been shifted, the display returns to the original display position before shifting. note: the value of the address counter (adc) goes to the one corresponding to the address 00 (hexadecimal) of the ddram). the execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 khz. rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 0 db 0 1 instruction code : rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 1 db 0 instruction code: : don't care
? semiconductor ML9044 34/54 3) entry mode setting (1) when the i/d is set, the cursor or blink shifts to the right by 1 character position (id= 1; increment) or to the left by 1 character position (i/d= 0; decrement) after an 8Cbit character code is written to or read from the ddram. at the same time, the address counter (adc) is also incremented by 1 (when i/d = 1; increment) or decremented by 1 (when i/d = 0; decrement). after a character pattern code is written to or read from the cgram, the address counter (adc) is incremented by 1 (when i/d = 1; increment) or decremented by 1 (when i/d = 0; decrement). also after data is written to or read from the abram, the address counter (adc) is incremented by 1 (when i/d = 1; increment) or decremented by 1 (when i/d = 0; decrement). (2) when s = 1, the cursor or blink stops and the entire display shifts to the left (i/d = 1) or to the right (i/d = 0) by 1 character position after a character code is written to the ddram. in the case of s = 1,when a character code is read from the ddram, when a character pattern data is written to or read from the cgram or when data is written to or read from the abram, normal read/write is carried out without shifting of the entire display. (the entire display does not shift, but the cursor or blink shifts to the right (i/d = 1) or to the left (i/d = 0) by 1 character position.) when s = 0, the display does not shift, but normal write/read is performed. note: the execution time of this instruction is 37 m s (maximum) at an oscillation frequency of 270 khz. 4) display mode setting (1) the d bit (db2) of this instruction determines whether or not to display character patterns on the lcd. when the d bit is 1, character patterns are displayed on the lcd. when the d bit is 0, character patterns are not displayed on the lcd and the cursor/blink setting is also canceled. note: unlike the display clear instruction, this instruction does not change the character code in the ddram and abram. (2 ) when the c bit (db1) is 0, the cursor turns off. when both the c and d bits are 1, the cursor turns on. (3) when the b bit (db0) is 0, blinking is canceled. when both the b and d bits are 1, blinking is performed. in the blinking mode, all dots including those of the cursor, the character pattern and the cursor are alternately displayed. note: the execution time of this instruction is 37 m s (maximum) at an oscillation frequency of 270khz. rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 1 db 1 i/d db 0 s instruction code: rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 1 db 2 d db 1 c db 0 b instruction code:
? semiconductor ML9044 35/54 5) cursor/display shift s/c = 0, r/l = 0 this instruction shifts left the cursor and blink positions by 1 (decrements the content of the adc by 1). s/c = 0, r/l = 1 this instruction shifts right the cursor and blink positions by 1 (increments the content of the adc by 1). s/c = 1, r/l = 0 this instruction shifts left the entire display by 1 character position. the cursor and blink positions move to the left together with the entire display. the arbitrator display is not shifted. (the content of the adc remains unchanged.) s/c = 1, r/l = 1 this instruction shifts right the entire display by 1 character position. the cursor and blink positions move to the right together with the entire display. the arbitrator display is not shifted. (the content of the adc remains unchanged.) in the 2Cline mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40 (27; hex) of the first line is shifted right. when the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from line 1 to line 2 or vice versa). note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. 6) function setting (1) when the dl bit (db4) of this instruction is 1, the data transfer to and from the cpu is performed once by the use of 8 bits db 7 to db 0 . when the dl bit (db4) of this instruction is 0, the data transfer to and from the cpu is performed twice by the use of 4 bits db 7 to db 4 . (2) the 2Cline display mode is selected when the n bit (db3) of this instruction is 1. the 1C line display mode is selected when the n bit is 0. (3) the character font represented by 5 7 dots is selected when the f bit (db2) of this instruction is 1. the character font represented by 5 10 dots is selected when the f bit is 1 and the n bit is 0. after the ML9044 is powered on, this initial setting should be carried out before execution of any instruction except the busy flag read. after this initial setting, no instructions other than the dl set instruction can be executed. in the serial i/f mode, dl setting is ignored. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 1 db 3 s/c db 2 r/l db 1 db 0 instruction code: : fdon't care rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 dl db 3 n db 2 f db 1 db 0 : don't care instruction code: nf number of display lines font size duty number of biases number of common signals 00 1 5 7 1/9 4 9 01 1 5 10 1/12 4 12 10 2 5 7 1/17 5 17 11 2 5 7 1/17 5 17
? semiconductor ML9044 36/54 7) cgram address setting rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 1 db 5 c 5 db 4 c 4 db 3 c 3 db 2 c 2 db 1 c 1 db 0 c 0 instruction code: rs 1 1 rs 0 0 r/ w 0 db 7 1 db 6 d 6 db 5 d 5 db 4 d 4 db 3 d 3 db 2 d 2 db 1 d 1 db 0 d 0 instruction code: rs 1 1 rs 0 1 r/ w 0 db 7 e 7 db 6 e 6 db 5 e 5 db 4 e 4 db 3 e 3 db 2 e 2 db 1 e 1 db 0 e 0 instruction code: this instruction sets the character data corresponding to the cgram address represented by the bits c5 to c0 (binary). the cgram addresses are valid until ddram or abram addresses are set. the cpu writes or reads character patterns starting from the one represented by the cgram address bits c 5 to c 0 set in the instruction code at that time. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. 8) ddram address setting this instruction sets the character data corresponding to the ddram address represented by the bits d6 to d0 (binary). the ddram addresses are valid until cgram or abram addresses are set. the cpu writes or reads character patterns starting from the one represented by the ddram address bits d6 to d0 set in the instruction code at that time. in the 1Cline mode (the n bit is 1), the ddram address represented by bits d6 to d0 (binary) should be in the range 00 to 4f in hexadecimal. in the 2Cline mode (the n bit is 2), the ddram address represented by bits d6 to d0 (binary) should be in the range 00 to 27 or 40 to 67 in hexadecimal. if an address other than above is input, the ML9044 cannot properly write a character code in or read it from the ddram. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. 9) ddram/abram/cgram data write this instruction writes data represented by bits e 7 to e 0 (binary) to ddram, abram or cgram. after data is written, the cursor, blink or display shifts according to the cursor/display shift instruction (see 5)). note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz.
? semiconductor ML9044 37/54 10) busy flag/address counter read (execution time: 1 m s) the bf bit (db7) of this instruction tells whether the ML9044 is busy in internal operation (bf = 1) or not (bf = 0). when the bf bit is 1, the ML9044 cannot accept any other instructions. before inputting a new instruction, check that the bf bit is 0. when the bf bit is 0, the ML9044 outputs the correct value of the address counter. the value of the address counter is equal to the ddram, abram or cgram address. which of the ddram, abram and cgram addresses is set in the counter is determined by the preceding address setting. when the bf bit is 1, the value of the address counter is not always correct because it may have been incremented or decremented by 1 during internal operation. 11) ddram/abram/cgram data read a character code (p 7 to p 0 ) is read from the ddram, displayCon data (p 7 to p 0 ) from the abram or a character pattern (p 7 to p 0 ) from the cgram. the ddram, abram or cgram is selected at the preceding address setting. after data is read, the address counter (adc) is incremented or decremented as set by the transfer mode setting instruction (see 3). note: conditions for reading correct data (1) the ddram, abram or cgram setting instruction is input before this data read instruction is input. (2) when reading a character code from the ddram, the cursor/display shift instruction (see 5) is input before this data read instruction is input. (3) when two or more consecutive ram data read instructions are executed, the following read data is correct. correct data is not output under conditions other than the cases (1), (2) and (3) above. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. rs 1 1 rs 0 0 r/ w 1 db 7 bf db 6 o 6 db 5 o 5 db 4 o 4 db 3 o 3 db 2 o 2 db 1 o 1 db 0 o 0 instruction code: rs 1 1 rs 0 1 r/ w 1 db 7 p 7 db 6 p 6 db 5 p 5 db 4 p 4 db 3 p 3 db 2 p 2 db 1 p 1 db 0 p 0 instruction code:
? semiconductor ML9044 38/54 expansion instruction codes the busy status of the ML9044 is rather longer than the cycle time of the cpu, since the internal processing of the ML9044 starts at a timing which does not affect the display on the lcd. in the busy status (busy flag is 1), the ml9041 executes the busy flag read instruction only. therefore, the cpu should ensure that the busy flag is 0 before sending an expansion instruction code to the ML9044. 1) arbitrator display line set this expansion instruction code sets the arbitrator display line. the relationship between the status of this bit and the common outputs is as follows: 2) contrast adjusting data write rs 1 0 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 0 db 4 0 db 3 0 db 2 0 db 1 1 db 0 as exparsion instruction codes: rs 1 0 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 f 4 db 3 f 3 db 2 f 2 db 1 f 1 db 0 f 0 exparsion instraction codes: csr duty as bit shift direction arbitrator's comon pin l 1/9 l com1 ? com9 com9 l 1/9 h com2 ? com9, com1 com1 l 1/12 l com1 ? com12 com12 l 1/12 h com2 ? com12, com1 com1 l 1/17 l com1 ? com17 com17 l 1/17 h com2 ? com17, com1 com1 h 1/9 l com9 ? com1 com1 h 1/9 h com8 ? com1, com9 com9 h 1/12 l com12 ? com1 com1 h 1/12 h com11 ? com1, com12 com12 h 1/17 l com17 ? com1 com1 h 1/17 h com16 ? com1, com17 com17 this instruction writes contrast adjusting data (f 4 to f 0 ) to the contrast register. after contrast adjusting data is written in the register, the potential (vlcd) output to the v 5 pin varies according to the data written. the vlcd becomes maximum when the content of the contrast register is 1f (hexadecimal) and becomes minimum when it is 00 (hexadecimal). note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz.
? semiconductor ML9044 39/54 3) contrast adjusting data read this instruction reads contrast adjusting data (g 4 to g 0 ) from the contrast register. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. 4) abram address setting this instruction sets the character data corresponding to the abram address represented by the bits h 4 to h 0 (binary). the abram addresses are valid until cgram or ddram addresses are set. the cpu writes or reads character patterns starting from the one represented by the abram address bits h 4 to h 0 set in the instruction code at that time. the abram address represented by bits h4 to h0 (binary) should be in the range 00 to 13 in hexadecimal. if an address other than above is input, the ML9044 cannot properly write a character code in or read it from the ddram. note: the execution time of this instruction is 37 m s at an oscillation frequency (osc) of 270 khz. rs 1 0 rs 0 0 r/ w 1 db 7 0 db 6 0 db 5 0 db 4 g 4 db 3 g 3 db 2 g 2 db 1 g 1 db 0 g 0 exparsion instruction code: rs 1 0 rs 0 0 r/ w 1 db 7 0 db 6 1 db 5 1 db 4 h 4 db 3 h 3 db 2 h 2 db 1 h 1 db 0 h 0 exparsion instruction code:
? semiconductor ML9044 40/54 lcd drive waveforms the com and seg waveforms (ac signal waveforms for display) vary according to the duty (1/ 9, 1/12 and 1/17 duties). see 1) to 3) below. the relationship between the duty ratio and the frame frequency is as follows: note: at an oscillation frequency (osc) of 270 khz (1) driving the lcd of one 24Ccharacter line (1/9 duty, csr = l, as = 0) under the conditions of the 1Cline display mode and the character font of 5 7 dots ? com 10 to com 17 output displayCoff common signals. duty ratio frame frequency 1/9 75.0hz 1/12 56.3hz 1/17 79.4hz com 1 character cursor arbitrator com 8 com 9 seg 1 seg 120 ML9044
? semiconductor ML9044 41/54 (2) driving the lcd of one 24Ccharacter line (1/12 duty, csr = l, as = 0) under the conditions of the 1Cline display mode and the character font of 5 10 dots ? com 13 to com 17 output displayCoff common signals. (3) driving the lcd of two 24Ccharacter line (1/17 duty, csr = l, as = 0) under the conditions of the 2Cline display mode and the character font of 5 7 dots com 1 com 11 com 12 seg 1 seg 120 msm9044 character cursor arbitrator com 1 com 8 seg 1 seg 120 msm9044 com 9 com 16 com 17 character cursor character cursor arbitrator
? semiconductor ML9044 42/54 examples of vlcd generation circuits ? with 1/4bias, a builtCin contrast adjusting circuit and a voltage multiplier ? with 1/5 bias, a builtCin contrast adjusting circuit and the v5 level input from an external circuit ML9044 beb v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd reference potential for voltage multiplien ML9044 beb v in v cc v c v 5in v 5 v 4 v 3b v 3a v 2 v 1 v dd v 5 level
? semiconductor ML9044 43/54 1) com and seg waveforms on 1/9 duty v dd 8 1 frame v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 com 1 (csr = l, as = l) com 2 (csr = l, as = h) com 9 (csr = h, as = l) com 8 (csr = h, as = h) (first character line) com 2 (csr = l, as = l) com 3 (csr = l, as = h) com 8 (csr = h, as = l) com 7 (csr = h, as = h) (second character line) com 8 (csr = l, as = l) com 9 (csr = l, as = h) com 2 (csr = h, as = l) com 1 (csr = h, as = h) (cursor line) com 9 (csr = l, as = l) com 1 (csr = l, as = h) com 1 (csr = h, as = l) com 9 (csr = h, as = h) (arbitrator line) 9 1 2 3 4 7 8 9 1 2 3 4 7 8 9 1 2 v dd v 1 v 2 , v 3b v 4 v 5 com 10 to com 17 v dd v 1 v 2 , v 3b v 4 v 5 seg display turning-off waveform display turning-on waveform
? semiconductor ML9044 44/54 2) com and seg waveforms on 1/12 duty v dd 1 frame v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 v dd v 1 v 2 , v 3b v 4 v 5 display turning-off waveform display turning-on waveform 11 com 1 (csr = l, as = l) com 2 (csr = l, as = h) com 12 (csr = h, as = l) com 11 (csr = h, as = h) (first character line) com 2 (csr = l, as = l) com 3 (csr = l, as = h) com 11 (csr = h, as = l) com 10 (csr = h, as = h) (second character line) com 11 (csr = l, as = l) com 12 (csr = l, as = h) com 2 (csr = h, as = l) com 1 (csr = h, as = h) (cursor line) com 12 (csr = l, as = l) com 1 (csr = l, as = h) com 1 (csr = h, as = l) com 12 (csr = h, as = h) (arbitrator line) 12 1 2 3 4 5 6 9 10 11 12 1 2 3 4 5 6 com 13 to com 17 seg
? semiconductor ML9044 45/54 3) com and seg waveforms on 1/17 duty v dd 16 1 frame v 1 v 2 v 3a ( v 3b ) v 4 17 1 2 3 4 5 6 7 8 9 10 11 12 13 16 17 1 2 display turning-off waveform display turning-on waveform 3 4 v 5 v dd v 1 v 2 v 3a ( v 3b ) v 4 v 5 v dd v 1 v 2 v 3a ( v 3b ) v 4 v 5 v dd v 1 v 2 v 3a ( v 3b ) v 4 seg v 5 v dd v 1 v 2 v 3a ( v 3b ) v 4 v 5 com 1 (csr = l, as = l) com 2 (csr = l, as = h) com 17 (csr = h, as = l) com 16 (csr = h, as = h) (first character line) com 2 (csr = l, as = l) com 3 (csr = l, as = h) com 16 (csr = h, as = l) com 15 (csr = h, as = h) (second character line) com 16 (csr = l, as = l) com 17 (csr = l, as = h) com 2 (csr = h, as = l) com 1 (csr = h, as = h) (corsor line) com 17 (csr = l, as = l) com 1 (csr = l, as = h) com 1 (csr = h, as = l) com 17 (csr = h, as = h) (arbitrator line)
? semiconductor ML9044 46/54 initial setting of instructions (a) data transfer from and to the cpu using 8 bits of db0 to db7 1) turn on the power. 2) wait for 15 ms or more after v dd has reached 2.5v or higher. 3) set 8 bits with the function setting instruction. 4) wait for 4.1 ms or more. 5) set 8 bits with the function setting instruction. 6) wait for 100 m s or more. 7) set 8 bits with the function setting instruction. 8) check the busy flag for no busy (or wait for 100 m s or more). 9) set 8 bits, number of lcd lines and font size with the function setting instruction. (after this, the number of lcd lines and the font size cannot be changed.) 10) check the busy flag for no busy. 11) execute the display mode setting instruction, display clear instruction, entry mode setting instruction and arbitrator display line setting instruction. 12) check the busy flag for no busy. 13) initialization is completed. an example of instruction code for 3), 5) and 7) (b) data transfer from and to the cpu using 8 bits of db4 to db7 1) turn on the power. 2) wait for 15 ms or more after v dd has reached 2.5v or higher. 3) set 8 bits with the function setting instruction. 4) wait for 4.1 ms or more. 5) set 8 bits with the function setting instruction. 6) wait for 100 m s or more. 7) set 8 bits with the function setting instruction. 8) check the busy flag for no busy (or wait for 100 m s or longer). 9) set 4 bits with the function setting instruction. 10) wait for 100 m s or longer. 11) set 4 bits, number of lcd lines and font size with the initial setting instruction. (after this, the number of lcd lines and the font size cannot be changed.) 12) check the busy flag for no busy. 13) execute the display mode setting instruction, display clear instruction, entry mode setting instruction and arbitrator display line setting instruction 14) check the busy flag for no busy. 15) initialization is completed. an example of instruction code for 3), 5) and 7) rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 1 db 3 db 2 db 1 db 0 : don't care rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 1
? semiconductor ML9044 47/54 an example of instruction code for 9) *: in 13), check the busy flag for no busy before executing each instruction. (c) data transfer from and to the cpu using the serial i/f 1) turn on the power. 2) wait for 15 ms or more after vdd has reached 2.5v or higher. 3) set number of lcd lines and font size with the function setting instruction. 4) execute the display mode setting instruction, the display clear instruction, the entry mode instruction and the arbitrator display line setting instruction. 5) check the busy flag for no busy. 6) initialization is completed. *: in 3) and 4), check the busy flag for no busy before executing each instruction. rs 1 1 rs 0 0 r/ w 0 db 7 0 db 6 0 db 5 1 db 4 0
? semiconductor ML9044 48/54 relationship between character codes and character patterns 00h 08h 10h 18h 20h 28h 30h 38h 01h 09h 11h 19h 21h 29h 31h 39h 02h 0ah 12h 1ah 22h 2ah 32h 3ah 03h 0bh 13h 1bh 23h 2bh 33h 3bh 04h 0ch 14h 1ch 24h 2ch 34h 3ch 05h 0dh 15h 1dh 25h 2dh 35h 3dh 06h 0eh 16h 1eh 26h 2eh 36h 3eh 07h 0fh 17h 1fh 27h 2fh 37h 3fh
? semiconductor ML9044 49/54 40h 48h 50h 58h 60h 68h 70h 78h 41h 49h 51h 59h 61h 69h 71h 79h 42h 4ah 52h 5ah 62h 6ah 72h 7ah 43h 4bh 53h 5bh 63h 6bh 73h 7bh 44h 4ch 54h 5ch 64h 6ch 74h 7ch 45h 4dh 55h 5dh 65h 6dh 75h 7dh 46h 4eh 56h 5eh 66h 6eh 76h 7eh 47h 4fh 57h 5fh 67h 6fh 77h 7fh
? semiconductor ML9044 50/54 80h 88h 90h 98h a0h a8h b0h b8h 81h 89h 91h 99h a1h a9h b1h b9h 82h 8ah 92h 9ah a2h aah b2h bah 83h 8bh 93h 9bh a3h abh b3h bbh 84h 8ch 94h 9ch a4h ach b4h bch 85h 8dh 95h 9dh a5h adh b5h bdh 86h 8eh 96h 9eh a6h aeh b6h beh 87h 8fh 97h 9fh a7h afh b7h bfh
? semiconductor ML9044 51/54 c0h c8h d0h d8h e0h e8h f0h f8h c1h c9h d1h d9h e1h e9h f1h f9h c2h cah d2h dah e2h eah f2h fah c3h cbh d3h dbh e3h ebh f3h fbh c4h cch d4h dch e4h ech f4h fch c5h cdh d5h ddh e5h edh f5h fdh c6h ceh d6h deh e6h eeh f6h feh c7h cfh d7h dfh e7h efh f7h ffh
? semiconductor ML9044 52/54 pad configuration pad layout chip size : 10.62 2.55mm chip thickness : 625 20 m m bump size (1) : 72 72 m m bump size (2) : 54 96 m m pad coordinates y x 182 183 62 189 56 1 63 55 pad symbol x ( m m) y ( m m) C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 v 1 v 2 v 3a v 3b v 4 v 5 v 5in v cc v c v in beb v dd csr ssr p /s v ss db 7 db 6 db 5 db 4 C5103 C4914 C4725 C4536 C4347 C4158 C3969 C3780 C3591 C3402 C3213 C3024 C2835 C2646 C2457 C2268 C2079 C1890 C1701 C1512 pad symbol x ( m m) y ( m m) db 3 db 2 db 1 db 0 e r/ w rs 0 rs 1 so si sht cs osc 2 osc r osc 1 t 3 t 2 t 1 com 1 com 2 C1323 C1134 C945 C756 C567 C378 C189 0 189 378 567 756 945 1134 1323 1512 1701 1890 2079 2268 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
? semiconductor ML9044 53/54 pad symbol x ( m m) y ( m m) com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 com 17 dummy dummy dummy dummy dummy 2457 2646 2835 3024 3213 3402 3591 3780 3969 4158 4347 4536 4725 4914 5103 5184 5184 5184 5184 5184 pad symbol x ( m m) y ( m m) seg 102 seg 101 seg 100 seg 99 seg 98 seg 97 seg 96 seg 95 seg 94 seg 93 seg 92 seg 91 seg 90 seg 89 seg 88 seg 87 seg 86 seg 85 seg 84 3486 3402 3318 3234 3150 3066 2982 2898 2814 2730 2646 2562 2478 2394 2310 2226 2142 2058 1974 1890 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 dummy 5184 1806 61 101 dummy 5184 1722 62 102 seg 120 4998 1638 63 103 seg 119 4914 1554 64 104 seg 118 4830 1470 65 105 seg 117 4746 1386 66 106 seg 116 4662 1302 67 107 seg 115 4578 1218 68 108 seg 114 4494 1134 69 109 seg 113 4410 1050 70 110 seg 112 4326 966 71 111 seg 111 4242 882 72 112 seg 110 4158 798 73 113 seg 109 4074 714 74 114 seg 108 3990 630 75 115 seg 107 3906 546 76 116 seg 106 3822 462 77 117 seg 105 3738 378 78 118 seg 104 3654 294 79 119 seg 103 3570 seg 64 seg 63 210 80 120 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C1099.8 C720 C480 C240 0 240 480 720 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 seg 83 seg 82 seg 81 seg 80 seg 79 seg 78 seg 77 seg 76 seg 75 seg 74 seg 73 seg 72 seg 71 seg 70 seg 69 seg 68 seg 67 seg 66 seg 65 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8
? semiconductor ML9044 54/54 pad symbol x ( m m) y ( m m) seg 62 seg 61 seg 60 seg 59 seg 58 seg 57 seg 56 seg 55 seg 54 seg 53 seg 52 seg 51 seg 50 seg 49 seg 48 seg 47 seg 46 seg 45 seg 44 seg 43 126 42 C42 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 seg 42 141 seg 41 142 seg 40 143 seg 39 144 seg 38 145 seg 37 146 seg 36 147 seg 35 148 seg 34 149 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 C126 C210 C294 C378 C462 C546 C630 C714 C798 C882 C966 C1050 C1134 C1218 C1302 C1386 C1470 C1554 C1638 C1722 C1806 C1890 C1974 C2058 C2142 C2226 pad symbol x ( m m) y ( m m) seg 27 seg 26 seg 25 seg 24 seg 23 seg 22 seg 21 seg 20 seg 19 seg 18 seg 17 seg 16 seg 15 seg 14 seg 13 seg 12 seg 11 seg 10 seg 9 seg 8 C2814 C2898 C2982 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 seg 7 176 seg 6 177 seg 5 178 seg 4 179 seg 3 180 seg 2 181 seg 1 182 dummy 183 dummy 184 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 1087.8 720 480 C3066 C3150 C3234 C3318 C3402 C3486 C3570 C3654 C3738 C3822 C3906 C3990 C4074 C4158 C4242 C4326 C4410 C4494 C4578 C4662 C4746 C4830 C4914 C4998 C5184 C5184 seg 33 150 C2310 dummy 185 240 C5184 seg 32 151 C2394 dummy 186 0 C5184 seg 31 152 C2478 dummy 187 C240 C5184 seg 30 153 C2562 dummy 188 C480 C5184 seg 29 154 C2646 dummy 189 C720 C5184 seg 28 155 C2730
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-62

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